1. Field of the Invention
The present invention relates to a semiconductor memory device and manufacturing method thereof. More particularly, the present invention relates to a memory merged logic (MML) semiconductor device having logic areas of a salicided dual gate structure and memory areas of a self-aligned contact (SAC) structure.
2. Description of the Related Art
With a recent trend toward high integration of semiconductor devices, miniaturization of various material layer patterns formed within a semiconductor device, increases of wafer diameters, and with a consumer""s demand for various products, System on Chip is in high demand in the semiconductor industry. Due to the increasing demand for System on Chip, merged semiconductor devices such as MML semiconductor devices in which a memory circuit and a logic circuit have been integrated together onto a single chip have been proposed.
In the fabrication of the MML semiconductor devices, high integration density of the memory circuits and high performance (high operational speed, for example) of the logic circuits are pressing requirements. To satisfy these requirements, many attempts at manufacturing an MML semiconductor device of a dual gate structure have been recently made by combining a self-aligned contact process adopted for improving the integration density of a memory device in the semiconductor memory device manufacturing field, and a self-aligned silicide (SALICIDE) process adopted for improving device characteristics, such as the operational speed of logic devices in logic device manufacturing field. For example, U.S. Pat. Nos. 5,998,252 and 6,015,730 disclose methods of manufacturing MML semiconductor devices through combination of SAC and SALICIDE processes.
However, according to U.S. Pat. No. 5,998,252 entitled, xe2x80x9cMethod of Salicide and SAC (Self-Aligned Contact) Integration,xe2x80x9d and U.S. Pat. No. 6,015,730 entitled, xe2x80x9cIntegration of SAC and Salicide Processes by Combining Hard Mask and Poly Definition,xe2x80x9d gate electrodes formed on the memory and logic areas are patterned by different etching processes, and the thickness of each are the same. Thus, since a gate electrode patterning process is performed separately in the memory area and in the logic area, this causes complications in a process. Furthermore, if the thickness of the gate electrode is the same in the logic and memory areas, there is a limitation to adopting the SAC process in the memory area as the integration density of the MML semiconductor device increases. This limitation is because an increase in the integration density of the MML semiconductor device reduces the distance between the gate electrodes formed on the memory area to below a given limit. In this case, due to degradation of a step coverage characteristic, a void may occur within a contact hole when the contact hole formed as a result of the SAC process is filled with a conductive material.
To solve the above problems, it is a feature of an embodiment of the present invention to provide a memory merged logic (MML) semiconductor device including a self-aligned contact (SAC) and a polycide gate electrode on a memory area, and salicided NMOS and PMOS gate electrodes and salicided source/drain region on logic area, wherein the height of the polycide gate electrode on the memory area is smaller than the heights of the salicided NMOS and PMOS gate electrodes on the logic area.
It is another feature of an embodiment of the present invention to provide a method of manufacturing the MML semiconductor device capable of improving the device integration density in a memory area by making the gate electrode on the memory area lower than that on a logic area while patterning the gate electrodes on the logic and memory areas at the same time.
It is still another feature of an embodiment of the present invention to provide a method of manufacturing the MML semiconductor device by which a self-aligned contact (SAC) process on a memory area and self-aligned silicide (SALICIDE) and dual gate processes on a logic area can be performed.
According to an embodiment of the present invention, there is provided an MML semiconductor device in which a memory area of a self-aligned contact structure and a logic area of a dual gate structure including n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) are integrated together. The memory area includes a polycide gate electrode, a hard mask pattern comprised of nitride materials which is formed on the polycide gate electrode, a spacer comprised of nitride materials formed along the sidewall of the polycide gate electrode, and a self-aligned contact which is formed between the adjacent spacers and electrically connected with an impurity implantation region formed on a semiconductor substrate. The logic area includes salicided NMOS and PMOS gate electrodes and salicided source/drain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.
Preferably, the polycide gate electrode includes a gate conductive pattern that is comprised of silicon and doped with conductive type impurities, and a silicide pattern. The gate conductive pattern may be a polysilicon pattern, and the silicide pattern may be a tungsten silicide pattern.
The NMOS gate electrode includes a gate conductive pattern that is comprised of silicon and doped with n-type impurities, and a silicide pattern formed by a self-aligned silicide (SALICIDE) process. The gate conductive pattern may be a polysilicon pattern, and the silicide pattern may be a cobalt silicide pattern.
Preferably, the PMOS gate electrode includes a gate conductive pattern that is comprised of silicon and doped with p-type impurities, and a silicide pattern formed by a SALICIDE process. The gate conductive pattern may be a polysilicon pattern, and the silicide pattern may be a cobalt silicide pattern.
The polycide gate electrode and the salicided NMOS and PMOS gate electrodes may include different kinds of silicide patterns.
A gate poly oxide layer is interposed between the sidewall of the polycide gate electrode and the spacer. The gate poly oxide layer, a nitride layer, and a medium temperature oxide (MTO) layer may be sequentially interposed in a direction from the sidewall of the polycide gate electrode to the spacer. The gate poly oxide layer and the medium temperature oxide layer may be sequentially interposed in a direction from the sidewall of the polycide gate electrode to the spacer.
An embodiment of the present invention also provides a method of manufacturing an MML semiconductor device including the following steps. First, (a) a semiconductor substrate on which a memory area and a logic area are defined, and on which an isolation layer and a gate oxide layer formed on an active region defined by the isolation layer have been formed is prepared. Second, (b) a gate conductive layer comprised of silicon is formed on the memory area and the logic area. Third, (c) the height of the gate conductive layer formed on the memory area is lowered and a predetermined conductive type of impurities is implanted into the lowered gate conductive layer. Fourth, (d) a silicide layer is formed only on the lowered gate conductive layer on the memory area using deposition and photolithography. In this case, the top surface of the silicide layer is lower than the top surface of the gate conductive layer formed on the logic area.
The third step, (c), additionally includes the following steps. First, (c1) a photoresist pattern is formed on the logic area. Second, (c2) the gate conductive layer formed on the memory area is etched by an etching process that uses the photoresist pattern as an etch mask and the gate conductive layer on the memory area is made lower than the gate conductive layer on the logic area. Third, (c3) an ion implantation process is performed to implant a predetermined conductive type of impurities into the lowered gate conductive layer on the memory area.
The fourth step, (d), additionally includes the following steps. First, (d1) a silicide layer is formed on the memory area and the logic area. Second, (d2) a photoresist pattern is formed on the silicide layer formed on the memory area. Third, (d3) the silicide layer formed on the logic area is removed using the photoresist pattern as an etch mask. Fourth, (d4) the photoresist pattern is removed.
The manufacturing method may additionally include the following steps after the fourth step, (d). Fifth, (e1) hard mask patterns comprised of nitride are formed on portions in which the gate electrodes will be formed on the memory area and the logic area. Sixth, (f1) the polycide gate electrode doped with predetermined impurities and the NMOS and PMOS gate electrodes not doped with impurities are formed on the memory area and the logic area, respectively. Seventh, (g1) lightly doped drain (LDD) structures having a conductive type of impurities required in the memory and logic areas are implemented by an ion implantation process. Eighth, (h1) a nitride layer and an oxide layer are sequentially formed over the entire surface of the semiconductor substrate in which the LDD structures have been implemented. Continuously, in the ninth step, (i1) the oxide layer formed only on the logic area is selectively removed. Tenth, (j1) a nitride layer formed on the logic area and a hard mask pattern formed on the NMOS and PMOS gate electrodes are removed by a wet etching process. The gate oxide layer is used as an etch stop layer in forming the polycide gate electrode and the NMOS and PMOS gate electrodes in the step (f1).
The manufacturing method may further still include the following steps. Eleventh, (k1), a spacer comprised of nitride is formed along the sidewall of the polycide gate electrode and the NMOS and PMOS gate electrodes. Twelfth, (l1), a predetermined conductive type of impurities is implanted into the memory area and the logic area to form source/drain regions, and at the same time a predetermined conductive type of impurities are implanted into the NMOS and PMOS gate electrodes. Thirteenth, (m1), the top surface of the NMOS and PMOS gate electrodes and the source/drain region formed on the logic area are exposed. Fourteenth, (n1), a silicide pattern is formed on the top surface of the NMOS and PMOS gate electrodes and the source/drain region on the logic area by a self-aligned suicide (SALICIDE) process. Continuously, in the fifteenth step, (o1) an interlayer dielectric is formed over the entire surface of the semiconductor substrate. Sixteenth, (p1) a self-aligned contact (SAC) electrically connected with the source/drain region formed on the memory area is formed by a SAC process.
Prior to the thirteenth step (m1), a silicide blocking layer, in which a medium temperature oxide layer and a nitride layer are sequentially stacked, may be selectively formed only on the memory area.
The manufacturing method may additionally include the alternative steps following the step (d). Fifth, (e2) a hard mask pattern comprised of nitride and a photoresist pattern is formed on portions in which the gate electrodes will be formed on the memory area and the logic area, respectively. Sixth, (f2) a polycide gate electrode doped with predetermined impurities and NMOS and PMOS gate electrodes not doped with impurities are formed on the memory are and logic area, respectively, by an etching process that uses the hard mask pattern and the photoresist pattern as an etch mask.
Preferably, the gate oxide layer is used as an etch stop layer in forming the polycide gate electrode and NMOS and PMOS gate electrodes in the alternate sixth step (f2).
The manufacturing method may additionally include the following alternate steps after the alternate sixth step (f2). Seventh, (g2) the photoresist pattern is removed. Eighth, (h2) the LDD structures having a conductive type required in the memory area and the logic area are implemented by an ion implantation process. Ninth, (i2) a spacer comprised of nitride on the sidewall of the polycide gate electrode and the NMOS and PMOS gate electrodes is formed. Tenth, (j2) source/drain regions are formed on the memory area and the logic area by an ion implantation process. Continuously, in the alternate eleventh step, (k2) a silicide blocking layer, in which a medium temperature oxide layer and a nitride layer are sequentially stacked, is selectively formed only on the memory area. Twelfth, (l2) the top surface of the NMOS and PMOS gate electrodes and the source/drain regions of the NMOS and PMOS are exposed, while protecting the memory area by the silicide blocking layer. Then, in the alternate thirteenth step, (m2) a SALICIDE process is performed to form a silicide pattern on the top surface of the NMOS and PMOS gate electrodes and the source/drain regions of the NMOS and PMOS. Fourteenth, (n2) an interlayer dielectric is formed over the entire surface of the semiconductor substrate. Fifteenth (o2), a SAC electrically connected with the source/drain region formed on the memory area is formed by a SAC process.
These and other features of the embodiments of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.